This Work Package is focused on the integration at the microsystem level technologies developed in WP3. Consistency of various technologies will be analyzed at each step of the project. A set of decision-making criteria will be proposed for comparing SOC and SIP approaches. The consortium will explore the possibilities offered by the integration of MEMS and ICs on SOI platforms:

• Horizontal integration of thin SOI MEMS devices and ICs designed on SOI 0.13 µm technology. Focus points are: (i) feasibility of a thin SOI accelerometer as well as thin nano-gap resonators, (ii) development of a piezoelectric switch compatible with piezoelectric resonator building at above-IC level, (iii) monolithic integration of ICs and MEMS on thick SOI though the development of a resonator for low-noise, low-power oscillators.

• Vertical co-integration is also explored by stacking blocks and functions that have been developed independently at separate levels (substrate level, interconnection, above-IC level, module level), using system in package (SIP) or possibly SoC. Vertical co-integration of passive components in particular is programmed, as well as co-integration of 0-assembly steps.

As far as wafer-level packaging is concerned two main strategies will be proposed in MIMOSA:

• Implementation of 0-assembly low cost packaging solutions through the use of typical microelectronic process steps: deposition, photo/litho and etching.
  
  
• Development of novel low cost functional packaging solutions taking advantage of new materials (polymer) and metallization techniques (antenna, pads).